A Boolean function ƒ(x1, x2, . . . , xn) is called a threshold function if there exist weights w1, w2, . . . , wn and a fixed threshold T such that
                              f          ⁡                      (                                          x                1                            ,                              x                2                            ,              …              ⁢                                                          ,                              x                n                                      )                          =                  {                                    if              ⁢                                                          ⁢                                                ∑                                      i                    =                    1                                    n                                ⁢                                                                  ⁢                                                      w                    i                                    ⁢                                      x                    i                                                                        ≥            T                                              (        1        )            
Without loss of generality, we may assume that wi and T are integers. A threshold function ƒ(x1, x2, . . . , xn) will be represented by [w1, w2, . . . , wn; T]. The following are the two examples of threshold function.
                              f          ⁡                      (                          a              ,              b              ,              c                        )                          =                ⁢                              a            ⋁            bc                    ⁢                                          ⁢                      (            2            )                                                  =                ⁢                              [                                                            w                  a                                =                2                            ,                                                w                  b                                =                1                            ,                                                                    w                    c                                    =                  1                                ;                                  T                  =                  2                                                      ]                    ⁢                                          ⁢                      (            3            )                                                  =                ⁢                              [                          2              ,              1              ,                              1                ;                2                                      ]                    ⁢                                          ⁢                      (            4            )                                                            g          ⁢                      (                          a              ,              b              ,              c              ,              d              ,              e                        )                          =                ⁢                  a          ⁢                                          ⁢                                    c              ⁡                              (                                  b                  ⋁                  d                  ⋁                  e                                )                                      ⋁                          de              ⁡                              (                                  a                  ⋁                  bc                                )                                      ⋁                          ab              ⁡                              (                                  d                  ⋁                  e                                )                                              ⁢                                          ⁢                      (            5            )                                                  =                ⁢                              [                                                            w                  a                                =                2                            ,                                                w                  b                                =                1                            ,                                                w                  c                                =                1                            ,                                                w                  d                                =                1                            ,                                                                    w                    e                                    =                  1                                ;                                  T                  =                  4                                                      ]                    .                                        =                ⁢                              [                          2              ,              1              ,              1              ,              1              ,                              1                ;                4                                      ]                    ⁢                                          ⁢                      (            6            )                              
A CMOS gate (or cell) refers to a combinational or sequential switching circuit that computes a certain Boolean function, constructed using Complementary Metal Oxide Semiconductor architecture
The CMOS network (or circuit or net-list) refers to a network of CMOS gates.
A threshold gate is a single primitive or a non-decomposable circuit that realizes a threshold function and one that physically embodies the comparison expressed in Equation (1). Therefore this excludes implementations that realize the threshold functions as simply Boolean functions using a network of Boolean primitives created using CMOS architecture.
The TLL or threshold logic latch cells refer to the circuits with a differential sense amplifier based architecture specifically designed to compute a threshold function. A TLL cell is essentially one possible implementation of the threshold gates.
A hybrid network is a network consisting of both CMOS and TLL cells.
Hybridization is defined as the process of converting a CMOS circuit into a Hybrid circuit in such a way that the functional and the timing behavior of the Hybrid circuit are same as that of the original CMOS circuit, while improving certain other characteristics such as power, area and delay.
As is evident from the example of the function g(a, b, c, d, e) above, a single threshold gate can implement a complex logic function, which in conventional logic design might require a multilevel network of several logic gates.
Since not all Boolean functions are threshold, an essential computation in the threshold logic synthesis is to determine whether or not a given Boolean function is a threshold function. Until recently this was done by solving an integer linear program (ILP) based on Equation (1). This approach is practical only for functions with small support sets and cannot be used when exploring a large gate level netlist for threshold functions. A new, fast approach for identifying a threshold function based on binary decision diagrams (BDD) may be used. Its efficiency allows it to be used repeatedly and to explore a given netlist much faster than the ILP based methods.
A substantial body of literature also exists on the circuit architectures for threshold gates. Among the various types, those based on differential logic such as DCSTL and SCSDL have been the most promising because they employ the conventional CMOS devices, require no special processing and have been shown to be very fast and low power. Unfortunately, the existing differential logic architectures are highly susceptible to failure due to noise and sizing them to achieve the same level of noise margin as TLL makes their power and delay unacceptably high.
A TLL cell in the library is a clocked sequential element that employs differential logic to compute a threshold function f(x1, x2 . . . xn) (both n and f vary from cell to cell) on a clock edge. Thus a library cell is referred to as a threshold logic latch (TLL) as it can be viewed as the integration of an edge triggered flip-flop and a threshold function. Although a TLL cell employs differential logic to implement a threshold function, it achieves the level of robustness with respect to noise and process variations that is required for high performance designs, and is superior to existing threshold logic architectures in terms of area, power and delay. Note that a TLL represents one embodiment of a general class of Differential mode Threshold Gates (DTGs). Since the present disclosure applies to any of such DTGs, we will use the term DTG to mean any embodiment of Differential mode Threshold Gates, such as TLLs.